1. Field of the Invention
The present invention relates to a flat-panel display device, and more particularly, to a flat-panel display device having test architecture.
2. Description of the Prior Art
Among existing display devices, the flat-panel display devices have gained utmost popularity. Furthermore, among the flat-panel display devices, the liquid crystal display (LCD) devices are widely applied in various electronic products such as computer monitors, mobile phones, personal digital assistants (PDAs), or flat-panel televisions due to thin appearance, low power consumption, and low radiation. In general, the LCD device comprises liquid crystal cells encapsulated between two substrates and a backlight module for providing a light source. The operation of an LCD device is featured by varying voltage drops between opposite sides of the liquid crystal cells for twisting the angles of the liquid crystal molecules of the liquid crystal cells so that the transparency of the liquid crystal cells can be controlled for illustrating images with the aid of the backlight module.
FIG. 1 is a schematic diagram showing a prior-art flat-panel display device having test architecture. As shown in FIG. 1, the flat-panel display device 100 comprises a bottom substrate 110, a top substrate 190 positioned on top of the bottom substrate 110, and a plurality of liquid crystal cells (not shown) encapsulated between the bottom substrate 110 and the top substrate 190. The top substrate 190 is a color filter for displaying color images of the flat-panel display device 100. The bottom substrate 110 comprises a bonding area 160 for attaching a flexible printed circuit board (not shown), a plurality of source driving integrated circuit (IC) mounting areas 120, a plurality of gate driving IC mounting areas 140, a plurality of data lines 130, a plurality of gate lines 150, a plurality of shorting bars 125, a horizontal bus 135, a vertical bus 155, and an image display area 195. The bonding area 160 comprises a plurality of bonding pads 165. Each bonding pad 165 is coupled to one horizontal transmission line of the horizontal bus 135 or one vertical transmission line of the vertical bus 155. The source driving IC mounting areas 120 and the gate driving IC mounting areas 140 are utilized for installing source driving ICs (not shown) and gate driving ICs (not shown) respectively. The horizontal bus 135 and the vertical bus 155 are disposed on the outer-lead-bonding (OLB) area of the bottom substrate 110 based on a wiring-on-array (WOA) arrangement.
In general, before the source driving ICs and the gate driving ICs are mounted respectively on the source driving IC mounting areas 120 and the gate driving IC mounting areas 140, an array test and a cell test are performed on the flat-panel display device 100 in order to check in advance whether any array wiring defect or any abnormal cell color display exists. Accordingly, the bottom substrate 110 is further disposed with a plurality of internal test pads 170 coupled to the shorting bars 125 for performing the array test and the cell test. The internal test pads 170 are further coupled to a plurality of external test pads 175 via a plurality of test signal transmission lines 172. As shown in FIG. 1, the test signal transmission lines 172 are crossed with the vertical bus 155 and parts of the horizontal transmission lines of the horizontal bus 135. For that reason, cross short-circuit defects are likely to occur at the intersections of the test signal transmission lines 172 and other related transmission lines, and therefore the circuit operation of the wiring-on-array may not function correctly due to the cross short-circuit defects. Furthermore, since the plurality of internal test pads 170 are disposed on the outer-lead-bonding area, the area available for disposing the vertical bus 155 and horizontal bus 135 is then reduced, which will increase wiring impedance and degrade signal transmission performance.
FIG. 2 is a schematic diagram showing the internal layout of the source driving IC mounting area in FIG. 1. As shown in FIG. 2, the source driving IC mounting area 120 is disposed with a plurality of connection pads 121 and at least two align marks 123. After finishing the array test and the cell test, a laser-cutting process is performed for cutting off the connections between the shorting bars 125 and the data lines 130 along the dotted line 124 with the aid of the align marks 123 to level the cutting position. The internal layout of the gate driving IC mounting area 140 is similar to the internal layout of the source driving IC mounting area 120, and for sake of brevity, further similar description is omitted. The source driving ICs and the gate driving ICs can be mounted respectively on the source driving IC mounting areas 120 and the gate driving IC mounting areas 140 only after finishing the laser-cutting process. However, while performing the laser-cutting process, lots of particles will come out and contaminate the bottom substrate 110 under processing, which may result in low product yields. Besides, the production cost of the prior-art flat-panel display devices is high following the requirement of the laser-cutting machine for performing the laser-cutting process.